Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

Preview PDF HTML

CC1020-RTR1 Datasheet(PDF) 21 Page - Texas Instruments

Part # CC1020-RTR1
Description  Low-Power RF Transceiver for Narrowband Systems
PDF  95 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CC1020-RTR1 Datasheet(HTML) 21 Page - Texas Instruments

Back Button CC1020-RTR1 Datasheet HTML 17Page - Texas Instruments CC1020-RTR1 Datasheet HTML 18Page - Texas Instruments CC1020-RTR1 Datasheet HTML 19Page - Texas Instruments CC1020-RTR1 Datasheet HTML 20Page - Texas Instruments CC1020-RTR1 Datasheet HTML 21Page - Texas Instruments CC1020-RTR1 Datasheet HTML 22Page - Texas Instruments CC1020-RTR1 Datasheet HTML 23Page - Texas Instruments CC1020-RTR1 Datasheet HTML 24Page - Texas Instruments CC1020-RTR1 Datasheet HTML 25Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 95 page
background image
PCLK
PDI
PSEL
Address
Read mode
6
5
4
3
2
1
0
T
SS
T
CL,min
T
CH,min
T
HS
R
PDO
7
6
5
4
3
2
1
0
Data byte
T
SH
CC1020
www.ti.com
SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
Figure 5-5. Configuration Registers Read Operation
Table 5-1. Serial Interface, Timing Specification(1)
PARAMETER
MIN
MAX
UNIT
CONDITION
FPCLK
PCLK, clock frequency
10
MHz
TCL,min
PCLK low pulse duration
50
ns
The minimum time PCLK must be low.
TCH,min
PCLK high pulse duration
50
ns
The minimum time PCLK must be high.
The minimum time PSEL must be low before
TSS
PSEL setup time
25
ns
positive edge of PCLK.
The minimum time PSEL must be held low
THS
PSEL hold time
25
ns
after the negative edge of PCLK.
TSH
PSEL high time
50
ns
The minimum time PSEL must be high.
The minimum time data on PDI must be ready
TSD
PDI setup time
25
ns
before the positive edge of PCLK.
The minimum time data must be held at PDI,
THD
PDI hold time
25
ns
after the positive edge of PCLK.
Trise
Rise time
100
ns
The maximum rise time for PCLK and PSEL
Tfall
Fall time
100
ns
The maximum fall time for PCLK and PSEL
(1)
The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% / 90% of VDD. The maximum load that this table is
valid for is 20 pF.
5.6
Signal Interface
The CC1020 can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-phase-
level) encoded data. CC1020 can also synchronize the data from the demodulator and provide the data
clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the MODEM register.
CC1020 can be configured for three different data formats: Synchronous NRZ mode, Transparent
Asynchronous UART mode, and Synchronous Manchester encoded mode.
Copyright © 2006–2015, Texas Instruments Incorporated
Detailed Description
21
Submit Documentation Feedback
Product Folder Links: CC1020



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link to Datasheet   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com