LP2995 datasheet(10/13 Pages) NSC

Part #	LP2995

Description	DDR Termination Regulator

PDF	13 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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10 / 13 page

PCB Layout Considerations

AVIN and PVIN should be tied together for optimal per-

formance. A local bypass capacitor should be placed as

close as possible to the PVIN pin.

GND should be connected to a ground plane with mul-

tiple vias for improved thermal performance.

SENSE should be connected to the VTT termination bus

at the point where regulation is required. For mother-

board applications an ideal location would be at the

center of the termination bus.

VDDQ can be connected remotely to the VDDQ rail

input at either the DIMM or the Chipset. This provides

the most accurate point for creating the reference volt-

age.

REF should be bypassed with a 0.01 µF or 0.1 µF

ceramic capacitor for improved performance. This ca-

pacitor should be located as close as possible to the

REF pin.

LP2995 Datasheet(PDF) 10 Page - National Semiconductor (TI)