LP2995

DDR Termination Regulator

General Description

The LP2995 linear regulator is designed to meet the JEDEC

SSTL-2 and SSTL-3 specifications for termination of DDR-

SDRAM. The device contains a high-speed operational am-

plifier to provide excellent response to load transients. The

output stage prevents shoot through while delivering 1.5A

continuous current and transient peaks up to 3A in the

application as required for DDR-SDRAM termination. The

LP2995 also incorporates a V

load regulation and a V

chipset and DDR DIMMS.

Patents Pending

Features

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Low output voltage offset

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Works with +5v, +3.3v and 2.5v rails

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Source and sink current

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Low external component count

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No external resistors required

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Linear topology

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Available in SO-8, PSOP-8 or LLP-16 packages

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Low cost and easy to use

Applications

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DDR Termination Voltage

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SSTL-2

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SSTL-3

Typical Application Circuit

20039302

July 2003

© 2003 National Semiconductor Corporation

DS200393

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