MB9AF154MB datasheet(112/133 Pages) SPANSION

112 / 133 page

D a t a S h e e t

April 28, 2015, MB9A150RB_DS706-00047-3v0-E

109

CONFIDENTIAL

12-bit A/D Converter

 Electrical Characteristics for the A/D Converter

(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)

Parameter

Symbol

name

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Integral Nonlinearity

± 2.4

± 4.5

LSB

Differential

Nonlinearity

± 2.3

± 2.5

LSB

Zero transition voltage

VZT

ANxx

± 7

± 15

Full-scale transition

voltage

VFST

ANxx

AVRH ± 7 AVRH ± 15

Conversion time*

2.0

μs

AVCC ≥ 2.7 V

4.0

1.8 V< AVCC < 2.7 V

1.65 V< AVCC < 1.8 V

Sampling time*

0.6

AVCC ≥ 2.7 V

1.2

1.8 V< AVCC < 2.7 V

3.0

1.65 V< AVCC < 1.8 V

Compare clock

cycle*

tCCK

100

1000

AVCC ≥ 2.7 V

200

1.8 V< AVCC < 2.7 V

500

1.65 V< AVCC < 1.8 V

State transition time to

operation permission

tSTT

1.0

μs

Analog input capacity

CAIN

9.4

Analog input resistor

RAIN

2.2

kΩ

AVCC ≥ 2.7 V

5.5

1.8 V< AVCC < 2.7 V

10.5

1.65 V< AVCC < 1.8 V

Interchannel disparity

LSB

Analog port input leak

current

ANxx

μA

Analog input voltage

ANxx

AVSS

AVRH

Reference voltage

AVRH

2.7

AVCC

AVCC ≥ 2.7 V

AVCC

AVCC < 2.7 V

*1: The conversion time is the value of sampling time (tS) + compare time (tC).

The condition of the minimum conversion time is the following.

AVCC ≥ 2.7 V, HCLK=40 MHz

sampling time: 0.6 μs, compare time: 1.4 μs

1.8 V < AVCC < 2.7 V, HCLK=40 MHz

sampling time: 1.2 μs, compare time: 2.8 μs

1.65 V < AVCC < 1.8 V, HCLK=40 MHz

sampling time: 3 μs, compare time: 7 μs

Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).

For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family

Peripheral Manual Analog Macro Part.

The register settings of the A/D Converter are reflected in the operation according to the APB bus clock

timing.

For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.

The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.

*2: A necessary sampling time changes by external impedance.

Ensure that it sets the sampling time to satisfy (Equation 1).

*3: The compare time (tC) is the value of (Equation 2).

MB9AF154MB Datasheet(PDF) 112 Page - SPANSION

MB9AF154MB Datasheet(HTML) 112 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL