2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

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5

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Serial Clock Frequency

(Note 12)

1.7

MHz

Hold Time, Repeated START

Condition (Sr)

160

ns

Low Period of the SCL Clock

320

ns

High Period of the SCL Clock

120

ns

Setup Time for a Repeated START

Condition (Sr)

160

ns

Data Hold Time

(Note 10)

0

150

ns

Data Setup Time

10

ns

Rise Time of SCL Signal

(Current Source Enabled)

20

80

ns

Rise Time of SCL Signal after

Acknowledge Bit

20

160

ns

Fall Time of SCL Signal

20

80

ns

Rise Time of SDA Signal

20

160

ns

Fall Time of SDA Signal

20

160

ns

Setup Time for STOP (P) Condition

160

ns

Capacitive Load for Each Bus Line

400

pF

Pulse Width of Spike Suppressed

(Notes 10 and 12)

0

10

ns

TIMING CHARACTERISTICS (Figure 1) (continued)

devices are configured for unipolar, single-ended inputs.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offsets have been calibrated.

Note 3: Offset nulled.

Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion

time does not include acquisition time. SCL is the conversion clock in the external clock mode.

Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.

Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a

0.01µF capacitor.

Note 9: Measured as for the MAX1237/MAX1239

VV

V

V

V

VV

FS

FS

REF

N

(.

)

( .

)

(.

.

)

36

27

21

36

27

−

−

−















