FT313HQ-R datasheet(39/67 Pages) ETC2

39 / 67 page

Document No.: FT_000589

FT313H USB2.0 HS Host Controller Datasheet Version 1.2

Clearance No.: FTDI# 318

Bit

Name

Type

Default value

Description

in the USB2.0 specification from the memory

to FIFO. Then, send the packet to the

transceiver.

TST_KSTA

R/W

1’b0

TEST_K

Upon writing a ‘1,’ the D+/D- are set to the

high-speed K state.

TST_JSTA

R/W

1’b0

TEST_J

Upon writing a ‘1,’ the D+/D- are set to the

high-speed J state.

Table 5-26 Test mode register

5.5.2 TESTPMSET1 register (address = 70h)

This parameter setting register is only used by test packet mode.

Bit

Name

Type

Default value

Description

[31:25]

Reserved

7’b0

[24: 8]

DMA_LEN

R/W

11’h000

DMA Length

The total bytes of the DMA controller will

move. The maximum length is 1024 – 1 Bytes.

[7: 2]

Reserved

6’b0

DMA_TYPE

R/W

1’b0

DMA Type

The transfer type of data moving

0: FIFO to Memory

1: Memory to FIFO

DMA_START

R/W

1’b0

DMA Start

This bit informs the DMA controller to initiate

the DMA transfer.

Table 5-27 Test mode parameter setting 1 register

5.5.3 TESTPMSET2 register (address = 74h)

This parameter setting register is only used by test packet mode.

Bit

Name

Type

Default value

Description

[31:0]

DMA_MADDR

R/W

32’b0

DMA Memory Address

The starting address of memory to request the

DMA transfer.

Table 5-28 Test parameter setting 2 register

FT313HQ-R Datasheet(PDF) 39 Page - List of Unclassifed Manufacturers

FT313HQ-R Datasheet(HTML) 39 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Datasheet Download

Link URL