CDPCLK4 datasheet(109/274 Pages) ALTERA

109 / 274 page

Chapter 6: I/O Features in the Cyclone III Device Family

6–11

I/O Standards

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 6–5 shows the single-ended I/O standards for OCT without calibration. The RS

shown is the intrinsic transistor impedance.

All I/O banks and I/O pins support impedance matching and series termination.

Dedicated configuration pins and JTAG pins do not support impedance matching or

series termination.

On-chip series termination is supported on any I/O bank. VCCIO and VREF must be

compatible for all I/O pins to enable on-chip series termination in a given I/O bank.

I/O standards that support different RS values can reside in the same I/O bank as

long as their VCCIO and VREF are not conflicting.

Impedance matching is implemented using the capabilities of the output driver and is

subject to a certain degree of variation, depending on the process, voltage, and

temperature.

f For more information about tolerance specification, refer to the Cyclone III Device Data

Sheet and Cyclone III LS Device Data Sheet chapters.

I/O Standards

The Cyclone III device family supports multiple single-ended and differential I/O

standards. Apart from 3.3-, 3.0-, 2.5-, 1.8-, and 1.5-V support, the Cyclone III device

family also supports 1.2-V I/O standards.

Figure 6–5. Cyclone III Device Family On-Chip Series Termination Without Calibration

Cyclone III Device Family

Driver Series Termination

Receiving

Device

VCCIO

GND

CDPCLK4 Datasheet(PDF) 109 Page - Altera Corporation