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CDPCLK4 Datasheet(PDF) 63 Page - Altera Corporation |
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CDPCLK4 Datasheet(HTML) 63 Page - Altera Corporation |
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63 / 274 page  Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family 5–3 Clock Networks July 2012 Altera Corporation Cyclone III Device Handbook Volume 1 PLL4_C1 —— —— ——— —— —— —— ——— v —— v PLL4_C2 —— —— ——— —— —— —— —— v — v —— PLL4_C3 —— —— ——— —— —— —— ——— v — v — PLL4_C4 —— —— ——— —— —— —— ——— — v — v DPCLK0 v — — — ——— —— —— —— ——— —— —— DPCLK1 — v —— ——— —— —— —— ——— —— —— DPCLK7 (4) CDPCLK0 , or CDPCLK7 (2), (5) —— v — ——— —— —— —— ——— —— —— DPCLK2 (4) CDPCLK1 , or CDPCLK2 (2), (5) —— — vv —— —— —— —— ——— —— —— DPCLK5 (4) DPCLK7 (2) —— —— — v —— —— —— —— — — — — — — DPCLK4 (4) DPCLK6 (2) —— —— —— v —— —— —— ——— —— —— DPCLK6 (4) CDPCLK5 , or CDPCLK6 (2), (5) —— —— ——— v — — — — — ——— —— —— DPCLK3 (4) CDPCLK4 , or CDPCLK3 (2), (5) —— —— ——— — vv — — — ——— —— —— DPCLK8 —— —— ——— —— — v —— ——— —— —— DPCLK11 —— —— ——— —— —— v — ——— —— —— DPCLK9 —— —— ——— —— —— — v ——— —— —— DPCLK10 —— —— ——— —— —— —— vv —— —— — DPCLK5 —— —— ——— —— —— —— —— v —— —— DPCLK2 —— —— ——— —— —— —— ——— v —— — DPCLK4 —— —— ——— —— —— —— ——— — v —— DPCLK3 —— —— ——— —— —— —— ——— —— vv Notes to Table 5–1: (1) EP3C5 and EP3C10 devices only have GCLK networks 0 to 9. (2) These pins apply to all devices in the Cyclone III device family except EP3C5 and EP3C10 devices. (3) EP3C5 and EP3C10 devices only have phase-locked loops (PLLs) 1 and 2. (4) This pin applies only to EP3C5 and EP3C10 devices. (5) Only one of the two CDPCLK pins can feed the clock control block. You can use the other pin as a regular I/O pin. Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 2 of 2) GCLK Network Clock Sources GCLK Networks (1) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 |
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