WM8953ECSSLASHRV datasheet(86/100 Pages) WOLFSON

86 / 100 page

WM8953

Production Data

PD, January 2009, Rev 4.0

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

TOCLK_RATE

Timeout Clock Rate

(Selects clock to be used for volume update timeout and

GPIO input de-bounce)

0 = SYSCLK / 221 (Slower Response)

1 = SYSCLK / 219 (Faster Response)

TOCLK_ENA

Timeout Clock Enable

(This clock is required for volume update timeout and GPIO

input de-bounce)

0 = disabled

1 = enabled

Reserved - Do Not Change

12:9

OPCLKDIV

[3:0]

0000b

GPIO Output Clock Divider

0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK / 16

1001 to 1111 = Reserved

8:5

1110b

Reserved - Do Not Change

4:1

BCLK_DIV

[3:0]

0100b

BCLK Frequency (Master Mode)

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0110 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 = SYSCLK / 32

1110 = SYSCLK / 44

1111 = SYSCL:K / 48

R06 (06h)

Clocking (1)

Reserved - Do Not Change

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = PLL output

R07 (07h)

Clocking (2)

CLK_FORCE

Forces Clock Source Selection

0 = Existing SYSCLK source (MCLK or PLL output) must be

active when changing to a new clock source.

1 = Allows existing MCLK source to be disabled before

changing to a new clock source.

WM8953ECS/RV Datasheet(PDF) 86 Page - Wolfson Microelectronics plc

WM8953ECS/RV Datasheet(HTML) 86 Page - Wolfson Microelectronics plc

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