WM8953ECSSLASHRV datasheet(63/100 Pages) WOLFSON

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Production Data

WM8953

PD, January 2009, Rev 4.0

DIGITAL AUDIO INTERFACE CONTROL

The register bits controlling audio data format, word length, left/right channel data source and TDM

are summarised in Table 33.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIFADCL_SRC

Left ADC Data Source Select

0 = Left ADC data is output on left channel

1 = Right ADC data is output on left channel

AIFADCR_SRC

Right ADC Data Source Select

0 = Left ADC data is output on right channel

1 = Right ADC data is output on right

channel

AIFADC_TDM

ADC TDM Enable

0 = Normal ADCDAT operation

1 = TDM enabled on ADCDAT

AIFADC_TDM_

CHAN

ADCDAT TDM Channel Select

0 = ADCDAT outputs data on slot 0

1 = ADCDAT output data on slot 1

AIF_BCLK_INV

BCLK Invert

0 = BCLK not inverted

1 = BCLK inverted

Right, left and I2S modes – LRCLK polarity

0 = normal LRCLK polarity

1 = invert LRCLK polarity

AIF_LRCLK_IN

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

6:5

AIF_WL

[1:0]

10b

Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

Note - see “Companding” for the selection of

8-bit mode.

R4 (04h)

4:3

AIF_FMT

[1:0]

10b

Digital Audio Interface Format

00 = Right justified

01 = Left justified

10 = I2S Format

11 = DSP Mode

Table 33 Audio Data Format Control

AUDIO INTERFACE OUTPUT AND GPIO TRISTATE

Table 34.

All GPIO pins and digital audio interface pins will be tristated by this function, regardless of the state

of other registers which control these pin configurations.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R9 (09h)

AIF_TRIS

Audio Interface and GPIO Tristate

0 = Audio interface and GPIO pins operate normally

1 = Tristate all audio interface and GPIO pins

Table 34 Tri-stating the Audio Interface and GPIO Pins

WM8953ECS/RV Datasheet(PDF) 63 Page - Wolfson Microelectronics plc

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