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WM8953ECS/RV Datasheet(PDF) 68 Page - Wolfson Microelectronics plc |
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WM8953ECS/RV Datasheet(HTML) 68 Page - Wolfson Microelectronics plc |
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68 / 100 page ![]() WM8953 Production Data w PD, January 2009, Rev 4.0 68 SYSCLK CONTROL MCLK may be inverted by setting register bit MCLK_INV. Note that it is not recommended to change the control bit MCLK_INV while the WM8953 is processing data as this may lead to clock glitches and signal pop and clicks. The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either MCLK or the PLL output. The selected source is divided by the SYSCLK pre-divider MCLK_DIV to generate SYSCLK. The selected source may also be adjusted by the MCLK_DIV divider. These register fields are described in Table 38. See “PLL” for more details of the Phase Locked Loop clock generator. The WM8953 supports glitch-free SYSCLK source selection. When both clock sources are running and SYSCLK_SRC is modified to select one of these clocks, a glitch-free clock transition will take place. The de-glitching circuit will ensure that the minimum pulse width will be no less than the pulse width of the faster of the two clock sources. When the initial clock source is to be disabled before changing to the new clock source, the CLK_FORCE bit must also be used to force the clock source transition to take place. In this case, glitch-free operation cannot be guaranteed. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 14 SYSCLK_SRC 0b SYSCLK Source Select 0 = MCLK 1 = PLL output 13 CLK_FORCE 0b Forces Clock Source Selection 0 = Existing SYSCLK source (MCLK or PLL output) must be active when changing to a new clock source. 1 = Allows existing MCLK source to be disabled before changing to a new clock source. 12:11 MCLK_DIV [1:0] 00b SYSCLK Pre-divider. Clock source (MCLK or PLL output) will be divided by this value to generate SYSCLK. 00 = Divide SYSCLK by 1 01 = Reserved 10 = Divide SYSCLK by 2 11 = Reserved R7 (07h) 10 MCLK_INV 0b MCLK Invert 0 = Master clock not inverted 1 = Master clock inverted Table 38 MCLK and SYSCLK Control |
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