AD9873JS datasheet(28/39 Pages) AD

28 / 39 page

REV. 0

AD9873

–28–

Figure 13. 16-Quadrature Modulation

Tx Signal Level Considerations

The quadrature modulator itself introduces a maximum gain of

3 dB in signal level. To visualize this, assume that both the I data

and Q data are fixed at the maximum possible digital value, x.

Then the output of the modulator, z, is:

z = [x cos(

ωt) – x sin(ωt)]

It can be shown that z assumes a maximum value of

() =

2 (a gain of +3 dB). However, if the same

number of bits were used to represent the z values, as is used to

represent the x values, an overflow would occur. To prevent this

possibility, an effective –3 dB attenuation is internally imple-

mented on the I and Q data path.

() =









12 12

The following example assumes a Pk/rms level of 10 dB:

Maximum Symbol Component Input Value =

(2047 LSBs – 0.2 dB) =

2000 LSBs

Maximum Complex Input rms Value =

2000 LSBs + 6 dB – Pk/rms(dB) = 1265 LSBs rms

Maximum Complex Input rms Value calculation uses both I and

Q symbol components which adds a factor of 2 (= 6 dB) to

the formula.

Table IV. I–Q Input Test Signals

Input Level

Modulator Output Level

Single-Tone (fc – f)

I = cos(f)

FS – 0.2 dB

FS – 3.0 dB

Q = cos(f + 90 ) = –sin(f)

FS – 0.2 dB

Single-Tone (fc + f)

I = cos(f)

FS – 0.2 dB

FS – 3.0 dB

Q = cos(f + 270 ) = sin(f)

FS – 0.2 dB

Dual-Tone (fc

I = cos(f)

FS – 0.2 dB

Q = cos(f + 180 ) = –cos(f) or Q = cos(f)

FS – 0.2 dB

If INV SINC filter is enabled, an insertion loss of ~1.4 dB (for low

frequencies) occurs at the DAC output (see Figure 12a, 12b).

Programming the AD9873 to single-tone transmit mode while

disabling the INV SINC filter (address 0Fh) generates a maximum

(FS) amplitude single tone with a frequency (fc) determined by

the associated frequency tuning word.

Table IV shows typical I–Q input test signals with amplitude levels

related to 12-bit full scale (FS).

Tx Throughput and Latency

Data inputs effect the output fairly quickly but remain effective

due to AD9873’s filter characteristics. Data transmit latency

through the AD9873 is easiest to describe in terms of fSYSCLK

clock cycles (4 fMCLK). The numbers quoted are when an effect

is first seen after an input value change.

Latency of I/Q data entering the data assembler (AD9873 input)

to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK

cycles). DC values applied to the data assembler input will take

up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate and

settle at the DAC output. Enabling the Inverse SINC Filter adds

only 2 fSYSCLK clock cycles latency.

Frequency hopping is accomplished via changing the PROFILE

input pins. The time required to switch from one frequency

to another is less than 234 fSYSCLK cycles with the Inverse SINC

Filter engaged. With the Inverse SINC Filter bypassed, the

latency drops to less than 232 fSYSCLK cycles (58.5 fMCLK cycles).

D/A Converter

A 12-bit digital-to-analog converter (DAC) is used to convert

the digitally processed waveform into an analog signal. The worst-

case spurious signals due to the DAC are the harmonics of the

fundamental signal and their aliases. (Please see the AD9851 data

sheet for a detailed explanation of aliased images.) The wideband

12-bit DAC in the AD9873 maintains spurious-free dynamic

range (SFDR) performance of 59 dBc up to fOUT = 42 MHz

and 54 dBc up to fOUT = 65 MHz. The conversion process will

produce aliased components of the fundamental signal at n

fSYSCLK

fCARRIER (n = 1, 2, 3). These are typically filtered with

an external RLC filter at the DAC output. It is important for

DAC

INV

SINC

FILTER

0dB

1.4dB

HBF + CIC

INTERPOLATOR

+0.2dB

HBF + CIC

INTERPOLATOR

+0.2dB

ATTENUATOR

–3dB

MODULATOR

3dB MAX

COMPLEX

DATA

INPUT

ATTENUATOR

–3dB

TWO'S COMPLEMENT FORMAT

Figure 14. Signal Level Contribution

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