| Electronic Components Datasheet Search |
|
MPC8343ECVRADDB Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8343ECVRADDB Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
|
13 / 79 page ![]() MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 13 RESET Initialization 5.1 RESET DC Electrical Characteristics Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8343EA. 5.2 RESET AC Electrical Characteristics Table 10 provides the reset initialization AC timing specifications of the MPC8343EA. Table 9. RESET Pins DC Electrical Characteristics1 Parameter Symbol Condition Min Max Unit Input high voltage VIH —2.0 OVDD +0.3 V Input low voltage VIL —–0.3 0.8 V Input current IIN —— ±5 μA Output high voltage2 VOH IOH = –8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.4 V Notes: 1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE. 2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins. Table 10. RESET Initialization Timing Specifications Parameter Min Max Unit Notes Required assertion time of HRESET or SRESET (input) to activate reset flow 32 — tPCI_SYNC_IN 1 Required assertion time of PORESET with stable clock applied to CLKIN when the MPC8343EA is in PCI host mode 32 — tCLKIN 2 Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the MPC8343EA is in PCI agent mode 32 — tPCI_SYNC_IN 1 HRESET/SRESET assertion (output) 512 — tPCI_SYNC_IN 1 HRESET negation to SRESET negation (output) 16 — tPCI_SYNC_IN 1 Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is in PCI host mode 4— tCLKIN 2 Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8343EA is in PCI agent mode 4— tPCI_SYNC_IN 1 Input hold time for POR configuration signals with respect to negation of HRESET 0— ns — Time for the MPC8343EA to turn off POR configuration signals with respect to the assertion of HRESET —4 ns 3 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |