M24LR64-R-DW6TSLASH2 datasheet(15/126 Pages) STMICROELECTRONICS

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M24LR64-R

Signal description

Doc ID 15170 Rev 8

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2.6

Supply voltage (VCC)

2.6.1

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 100). In order to

secure a stable DC supply voltage, it is recommended to decouple the VCC line with a

suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package

pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal I²C write cycle (tW).

2.6.2

Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not

vary faster than 1V/µs.

2.6.3

Device reset

In order to prevent inadvertent write operations during power-up, a power-on reset (POR)

circuit is included. At power-up (continuous rise of VCC), the device does not respond to any

instruction until VCC has reached the power-on reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Table 100). When VCC passes

over the POR threshold, the device is reset and enters the Standby Power mode, however,

the device must not be accessed until VCC has reached a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range.

In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops

below the power-on reset threshold voltage, the device stops responding to any instruction

sent to it.

2.6.4

Power-down conditions

During power-down (continuous decay of VCC), the device must be in Standby Power mode

(mode reached after decoding a Stop condition, assuming that there is no internal write

cycle in progress).

Figure 4.

Maximum RP value versus bus parasitic capacitance (C) for an I

2C bus

100

1000

Bus line capacitor (pF)

fC = 400 kHz, tLOW = 1.3 µs

Rbus x Cbus time

constant must be less than

500 ns

I²C bus

master

M24xxx

Rbus

VCC

Cbus

SCL

SDA

ai14796

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