M24LR64-R-MB6TSLASH2 datasheet(50/126 Pages) STMICROELECTRONICS

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M24LR64-R to VCD frames

M24LR64-R

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Doc ID 15170 Rev 8

M24LR64-R to VCD frames

Frames are delimited by an SOF and an EOF. They are implemented using code violation.

Unused options are reserved for future use. For the low data rate, the same subcarrier

frequency or frequencies is/are used. In this case the number of pulses is multiplied by 4.

For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.

12.1

SOF when using one subcarrier

12.2

High data rate

The SOF includes an unmodulated time of 56.64 µs, followed by 24 pulses at 423.75 kHz

(fC/32), and a logic 1 that consists of an unmodulated time of 18.88 µs followed by 8 pulses

at 423.75 kHz as shown in Figure 35.

Figure 35.

Start of frame, high data rate, one subcarrier

For the Fast commands, the SOF comprises an unmodulated time of 28.32 µs, followed by

12 pulses at 423.75 kHz (fC/32), and a logic 1 that consists of an unmodulated time of

9.44µs followed by 4 pulses at 423.75 kHz as shown in Figure 36.

Figure 36.

Start of frame, high data rate, one subcarrier x2

12.3

Low data rate

The SOF comprises an unmodulated time of 226.56 µs, followed by 96 pulses at 423.75 kHz

(fC/32), and a logic 1 that consists of an unmodulated time of 75.52 µs followed by 32 pulses

at 423.75 kHz as shown in Figure 37.

Figure 37.

Start of frame, low data rate, one subcarrier

113.28µs

ai12078

37.76µs

56.64µs

ai12079

18.88µs

453.12µs

ai12080

151.04µs

M24LR64-R-MB6T/2 Datasheet(PDF) 50 Page - STMicroelectronics