M24LR64-R-MB6TSLASH2 datasheet(33/126 Pages) STMICROELECTRONICS

Part #	M24LR64-R-MB6T/2

Description	64 Kbit EEPROM with password protection & dual interface: 400kHz I짼C serial bus & ISO 18000-3 mode 1 RF protocol at 13.56MHz

PDF	126 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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33 / 126 page

M24LR64-R

I2C device operation

Doc ID 15170 Rev 8

33/126

5.9

Minimizing system delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum I²C write time (tw) is

shown in Table 104, but the typical time is shorter. To make use of this, a polling sequence

can be used by the bus master.

The sequence, as shown in Figure 12, is:

Initial condition: a write cycle is in progress.

Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

M24LR64-R-MB6T/2 Datasheet(PDF) 33 Page - STMicroelectronics