M24LR64-R-MB6TSLASH2 datasheet(17/126 Pages) STMICROELECTRONICS

Part #	M24LR64-R-MB6T/2

Description	64 Kbit EEPROM with password protection & dual interface: 400kHz I짼C serial bus & ISO 18000-3 mode 1 RF protocol at 13.56MHz

PDF	126 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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17 / 126 page

M24LR64-R

User memory organization

Doc ID 15170 Rev 8

17/126

User memory organization

The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5.

Figure 7 shows the memory sector organization. Each sector can be individually read-

and/or write-protected using a specific password command. Read and write operations are

possible if the addressed data are not in a protected sector.

The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier

(UID). The UID is compliant with the ISO 15963 description, and its value is used during the

anticollision sequence (Inventory). This block is not accessible by the user and its value is

written by ST on the production line.

The M24LR64-R includes an AFI register that stores the application family identifier, and a

DSFID register that stores the data storage family identifier used in the anticollision

algorithm.

The M24LR64-R has four additional 32-bit blocks that store an I2C password plus three RF

password codes.

Figure 6.

Block diagram

EEPROM

Latch

Logic

I2C

RF VCC

Contact VCC

SCL

SDA

VSS

VCC

AC0

AC1

Power management

ai15123

M24LR64-R-MB6T/2 Datasheet(PDF) 17 Page - STMicroelectronics