MPC8535EBVTATH datasheet(86/126 Pages) FREESCALE

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MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

I2C

Freescale Semiconductor

Figure 51 provides the AC test load for the I

2C.

Figure 51. I2C AC Test Load

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs—

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL

0.1

× OVDD

—V

—

Noise margin at the HIGH level for each connected device

(including hysteresis)

VNH

0.2

× OVDD

—V

—

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing

(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the

high (H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8535E provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

When the MPC8535E acts as the I2C bus master while transmitting, the MPC8535E drives both SCL and SDA. As long as the

load on SCL and SDA are balanced, the MPC8535E would not cause unintended generation of Start or Stop condition.

Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time

is required for the MPC8535E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register

to ensure both the desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C

SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default

setting of 0x10 (decimal 16):

I2C Source Clock Frequency

333 MHz

266 MHz

200 MHz

133 MHz

FDR Bit Setting

0x2A

0x05

0x26

0x00

Actual FDR Divider Selected

896

704

512

384

Actual I2C SCL Frequency Generated

371 KHz

378 KHz

390 KHz

346 KHz

For details of the I2C frequency calculation, refer to

Determining the I2C Frequency Divider Ratio for SCL (AN2919). Note that

the I2C Source Clock Frequency is half of the CCB clock frequency for the MPC8535E.

3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

Table 64. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Table 63).

Parameter

Symbol 1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

MPC8535EBVTATH Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc

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