MPC8535EBVTATH datasheet(52/126 Pages) FREESCALE

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MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management

Freescale Semiconductor

Figure 26 shows the RMII transmit AC timing diagram.

Figure 26. RMII Transmit AC Timing Diagram

2.9.2.7.2

RMII Receive AC Timing Specifications

Rise time TSECn_TX_CLK (20%–80%)

tRMTR

1.0

—

2.0

Fall time TSECn_TX_CLK (80%–20%)

tRMTF

1.0

—

2.0

TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay

tRMTDX

2.0

—

10.0

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX

symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid

(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock

of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

Table 37. RMII Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

TSECn_RX_CLK clock period

tRMR

15.0

20.0

25.0

TSECn_RX_CLK duty cycle

tRMRH

TSECn_RX_CLK peak-to-peak jitter

tRMRJ

—

250

Rise time TSECn_RX_CLK (20%–80%)

tRMRR

1.0

—

2.0

Table 36. RMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

TSECn_TX_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

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