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MPC8535EBVTATH Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc |
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MPC8535EBVTATH Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 126 page ![]() Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 47 Figure 21 shows the MII receive AC timing diagram. Figure 21. MII Receive AC Timing Diagram 2.9.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 2.9.2.4.1 TBI Transmit AC Timing Specifications Table 32 provides the TBI transmit AC timing specifications. Table 32. TBI Transmit AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition Symbol 1 Min Typ Max Unit GTX_CLK clock period tTTX —8.0 — ns GTX_CLK duty cycle tTTXH/tTTX 40 — 60 % GTX_CLK to TCG[9:0] delay time tTTKHDX 2 1.0 — 5.0 ns GTX_CLK rise (20%–80%) tTTXR —— 1.0 ns GTX_CLK fall time (80%–20%) tTTXF —— 1.0 ns Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Data valid tTTKHDV to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max Hold) RX_CLK RXD[3:0] tMRDXKL tMRX tMRXH tMRXR tMRXF RX_DV RX_ER tMRDVKH Valid Data |
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