MPC8378EVRALDA datasheet(26/126 Pages) FREESCALE

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MPC8378E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Change in VOS between “0” and

“1”

VOS

——

—

Output current on short to GND

ISA, ISB

——

—

Note:

1 This will not align to DC-coupled SGMII. XV

DD_SRDS-Typ =1.0 V.

2 |V

OD|=|VSD_TXn -VSD_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p =2 × |VOD|.

3 The |V

OD| value shown in the table assumes the following transmit equalization setting in SRDSnCR0[DDPA] and

SRDS

nCR0[TXEQA] for lane A, and SRDSnCR0[DDPE] and SRDSnCR0[TXEQE] for lane E.

•

DPPA or DPPE bit is set to zero (selecting the full VDD-DIFF-p-p amplitude – power up default);

•

TXEQA or TXDQE is set based on the equalization setting shown in table.

4 V

OS is also referred to as output common mode voltage.

The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS-Typ = 1.0 V, no common mode offset variation

(VOS = 500 mV), SerDes1 transmitter is terminated with 100-Ω differential load between SD_TXn and SD_TXn.

Table 26. SGMII DC Receiver Electrical Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Supply voltage

(L1_SDAVDD_0, L1_XCOREVDD)

XVDD_SRDS

0.95

1.0

1.05

—

DC input voltage range

—

N/A

—

Input differential voltage

SEIC

x = 01

SEIC

x = 00

VRX_DIFFp-p

100

175

—1200

2, 4

Loss of signal threshold

SEIC

x = 01

SEIC

x = 00

VLOS

—

100

175

3, 4

Input AC common mode voltage

VCM_ACp-p

—

100

Receiver differential input

impedance

ZRX_DIFF

100

120

—

Receiver common mode input

impedance

ZRX_CM

—

Common mode input voltage

VCM

—Vxcorevss

—V

Note:

1 Input must be externally AC-coupled.

2 V

RX_DIFFp-p is also referred to as peak to peak input differential voltage.

3 The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI

Express Differential Receiver (RX) Input Specifications section for further explanation.

4 The SEICx shown in the table refers to SRDSnCR[SEICA] for lane A and SRDSnCR[SEICE] for lane E.

5 V

CM_ACp-p is also referred to as peak to peak AC common mode voltage.

6 On-chip termination to SGND_SRDSn (xcorevss).

Table 25. SGMII DC Transmitter Electrical Characteristics (continued)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

MPC8378EVRALDA Datasheet(PDF) 26 Page - Freescale Semiconductor, Inc

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