M30620FCAFP datasheet(496/615 Pages) RENESAS

496 / 615 page

Power Control

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-179

2.15.3 Wait Mode Set-Up

Figure 2.15.6. Example of wait mode set-up

Settings and operation for entering wait mode are described here.

(1) Enables the interrupt used for returning from wait mode.

(2) Sets the interrupt enable flag (I flag) to “1”.

(3) Clears the protection and changes the content of the system clock control register.

(4) Executes the WAIT instruction.

Operation

Wait

(3) Canceling protect

Protect register [Address 000A16]

PRCR

Enables writing to system clock control registers 0 and 1

(addresses 000616 and 000716)

1 : Write-enabled

(4) WAIT instruction

(3) Control of CPU clock

Note 1: When switching the system clock, it is necessary to wait for the oscillation to stabilize.

Note 2: Set the WAIT peripheral function clock stop bit to “0” when the system clock select bit is “1”.

WAIT peripheral function clock stop bit (Note 2)

0 : Do not stop f1, f8, f32 in wait mode

1 : Stop f1, f8, f32 in wait mode

Port XC select bit

0 : I/O port

1 : XCIN-XCOUT generation

Main clock (XIN-XOUT) stop bit

0 : On

1 : Off

Main clock division select bit 0

0 : CM16 and CM17 valid

1 : Division by 8 mode

System clock select bit (Note 1)

0 : XIN, XOUT

1 : XCIN, XCOUT

System clock control register 0

[Address 000616] CM0

System clock control register 1

[Address 000716] CM1

0000

Reserved bit

Must always be set to “0”

Main clock division select bit

0 0 : No division mode

0 1 : Division by 2 mode

1 0 : Division by 4 mode

1 1 : Division by 16 mode

b7 b6

Interrupt control register

TBiIC(i=3 to 5)

[Address 004516 to 004716]

BCNIC

[Address 004A16]

KUPIC

[Address 004D16]

SiTIC(i=0 to 2)

[Address 005116, 005316, 004F16]

SiRIC(i=0 to 2)

[Address 005216, 005416, 005016]

TAiIC(i=0 to 4)

[Address 005516 to 005916]

TBiIC(i=0 to 2)

[Address 005A16 to 005C16]

(1) Setting interrupt to cancel wait mode

Make sure that the interrupt priority

level of the interrupt which is used

to cancel the wait mode is higher

than the processor interrupt priority

(IPL) of the routine where the

WAIT instruction is executed.

Interrupt priority level select bit

INTiIC(i=3)

[Address 004416]

SiIC/INTjIC (i=4, 3)

[Address 004816, 004916]

(j=3, 4)

[Address 004816, 004916]

INTiIC(i=0 to 2)

[Address 005D16 to 005F16]

Make sure that the interrupt priority level of the

interrupt which is used to cancel the wait mode is

higher than the processor interrupt priority (IPL) of

the routine where the WAIT instruction is executed.

Interrupt priority level select bit

Reserved bit

Must always be set to “0”

(2) Interrupt enable flag (I flag)

“1”

Insert at least four NOPs after the WAIT instruction is executed.

M30620FCAFP Datasheet(PDF) 496 Page - Renesas Technology Corp

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