M30620FCAFP datasheet(495/615 Pages) RENESAS

495 / 615 page

Power Control

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-178

2.15.2 Stop Mode Set-Up

(1) Enables the interrupt used for returning from stop mode.

(2) Sets the interrupt enable flag (I flag) to “1”.

(3) Clearing the protection and setting all clock stop control bit to “1” stops oscillation and causes

the processor to go into stop mode.

Operation

Settings and operation for entering stop mode are described here.

Figure 2.15.5. Example of stop mode set-up

All clocks off (stop mode)

(3) Canceling protect

Protect register [Address 000A16]

PRCR

Enables writing to system clock control registers 0 and 1

(addresses 000616 and 000716)

1 : Write-enabled

(3) All clocks off (stop mode)

System clock control register [Address 000716]

CM1

0000

Reserved bit

Must always be set to “0”

All clock stop control bit

1 : All clocks off (stop mode)

Interrupt control register

TBiIC(i=3 to 5)

[Address 004516 to 004716]

BCNIC

[Address 004A16]

KUPIC

[Address 004D16]

SiTIC(i=0 to 2)

[Address 005116, 005316, 004F16]

SiRIC(i=0 to 2)

[Address 005216, 005416, 005016]

TAiIC(i=0 to 4)

[Address 005516 to 005916]

TBiIC(i=0 to 2)

[Address 005A16 to 005C16]

(1) Setting interrupt to cancel stop mode

Make sure that the interrupt priority

level of the interrupt which is used to

cancel the wait mode is higher than

the processor interrupt priority(IPL) of

the routine where the WAIT

instruction is executed.

Interrupt priority level select bit

INTiIC(i=3)

[Address 004416]

SiIC/INTjIC(i=4, 3)

[Address 004816, 004916]

(j=3, 4)

[Address 004816, 004916]

INTiIC(i=0 to 2)

[Address 005D16 to 005F16]

Make sure that the interrupt priority level of the

interrupt which is used to cancel the wait mode is

higher than the processor interrupt priority(IPL) of

the routine where the WAIT instruction is executed.

Interrupt priority level select bit

Reserved bit

Must always be set to “0”

System clock control register

[Address 000616] CM0

(3) Setting operation clock after returning from stop mode

Main clock (XIN-XOUT) stop bit

System clock select bit

XIN, XOUT

As this register becomes setting mentioned above when

operating with XIN (count source of BCLK is XIN),

the user does not need to set it again.

System clock control register 0

[Address 000616] CM0

XCIN-XCOUT generation

Port XC select bit

System clock select bit

XCIN, XCOUT

As this register becomes setting mentioned above when operating with XCIN

(count source of BCLK is XCIN), the user does not need to set it again.

When operating with XIN, set port Xc select bit to “1” before setting system clock

select bit to “1”. The both bits cannot be set at the same time.

(When operating with XCIN after returning)

(When operating with XIN after returning)

(2) Interrupt enable flag (I flag)

“1”

Insert at least four NOPs after the instruction that sets the all clock stop control bit to “1”.

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