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H8SX1663 Datasheet(PDF) 694 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 694 Page - Renesas Technology Corp |
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694 / 1158 page  Section 14 Watchdog Timer (WDT) Rev.1.00 Jun. 07, 2006 Page 642 of 1102 REJ09B0294-0100 Overflow Interrupt control WOVI (interrupt request signal) Internal reset signal* WDTOVF Reset control RSTCSR TCNT TCSR P φ/2 P φ/64 P φ/128 P φ/512 P φ/2048 P φ/8192 P φ/32768 P φ/131072 Clock Clock select Internal clocks Bus interface Module bus TCSR: TCNT: RSTCSR: Note: * An internal reset signal can be generated by the RSTCSR setting. Timer control/status register Timer counter Reset control/status register WDT [Legend] Figure 14.1 Block Diagram of WDT 14.2 Input/Output Pin Table 14.1 shows the WDT pin configuration. Table 14.1 Pin Configuration Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs a counter overflow signal in watchdog timer mode |
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