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H8SX1663 Datasheet(PDF) 695 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 695 Page - Renesas Technology Corp |
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695 / 1158 page ![]() Section 14 Watchdog Timer (WDT) Rev.1.00 Jun. 07, 2006 Page 643 of 1102 REJ09B0294-0100 14.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 14.6.1, Notes on Register Access. • Timer counter (TCNT) • Timer control/status register (TCSR) • Reset control/status register (RSTCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. 7 OVF 0 R/(W)* 6 WT/ IT 0 R/W 5 TME 0 R/W 4 1 R 3 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W |
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