H8SX1663 datasheet(697/1158 Pages) RENESAS

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Section 14 Watchdog Timer (WDT)

Rev.1.00 Jun. 07, 2006 Page 645 of 1102

REJ09B0294-0100

14.3.3

Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects

the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the

RES pin,

but not by the WDT internal reset signal caused by WDT overflows.

WOVF

R/(W)*

RSTE

R/W



R/W



Bit

Bit Name

Initial Value

R/W

Note: * Only 0 can be written to this bit, to clear the flag.

Bit

Bit Name

Initial

Value

R/W

Description

WOVF

R/(W)* Watchdog Timer Overflow Flag

This bit is set when TCNT overflows in watchdog timer

mode. This bit cannot be set in interval timer mode, and

only 0 can be written.

[Setting condition]

When TCNT overflows (changed from H'FF to H'00) in

watchdog timer mode

[Clearing condition]

Reading RSTCSR when WOVF = 1, and then writing 0 to

WOVF

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

RSTE

R/W

Reset Enable

Specifies whether or not this LSI is internally reset if

TCNT overflows during watchdog timer operation.

0: LSI is not reset even if TCNT overflows (Though this

LSI is not reset, TCNT and TCSR in WDT are reset)

1: LSI is reset if TCNT overflows

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