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H8SX1663 Datasheet(PDF) 630 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 630 Page - Renesas Technology Corp |
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630 / 1158 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev.1.00 Jun. 07, 2006 Page 578 of 1102 REJ09B0294-0100 10.10.8 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.50 shows the timing in this case. TGR P φ Input capture signal Address TGR address Read T 1 T 2 TGR read cycle XM M Internal data bus Figure 10.50 Conflict between TGR Read and Input Capture |
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