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H8SX1663 Datasheet(PDF) 633 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 633 Page - Renesas Technology Corp |
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633 / 1158 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev.1.00 Jun. 07, 2006 Page 581 of 1102 REJ09B0294-0100 10.10.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. Counter clear signal H'0000 P φ TCNT input clock TCNT TGF flag TCFV flag H'FFFF Disabled Figure 10.53 Conflict between Overflow and Counter Clearing |
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