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H8SX1663 Datasheet(PDF) 626 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 626 Page - Renesas Technology Corp |
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626 / 1158 page  Section 10 16-Bit Timer Pulse Unit (TPU) Rev.1.00 Jun. 07, 2006 Page 574 of 1102 REJ09B0294-0100 10.10 Usage Notes 10.10.1 Module Stop State Setting Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop state. For details, refer to section 23, Power-Down Modes. 10.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.45 shows the input clock conditions in phase counting mode. TCLKA (TCLKC) TCLKB (TCLKD) Overlap Phase difference Pulse width Note: Phase difference, Overlap ≥ 1.5 states Pulse width ≥ 2.5 states Pulse width Phase difference Overlap Pulse width Pulse width Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode |
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