HD6432138SW datasheet(221/1061 Pages) RENESAS

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Section 7 Data Transfer Controller [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 167 of 1004

REJ09B0301-0400

A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence

between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number

generated by the interrupt controller in each case.

For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions

such as BSET and BCLR. For the initial setting only, however, when multiple activation sources

are set at one time, it is possible to disable interrupts and write after executing a dummy read on

the relevant register.

7.2.8

DTC Vector Register (DTVECR)

SWDTE

R/(W)*

DTVEC6

R/W

DTVEC5

R/W

DTVEC4

R/W

DTVEC3

R/W

DTVEC0

R/W

DTVEC2

R/W

DTVEC1

R/W

A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1

is read.

Bit

Initial value

Read/Write

Note: *

DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by

software, and sets a vector number for the software activation interrupt.

DTVECR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—DTC Software Activation Enable (SWDTE): Specifies enabling or disabling of DTC

software activation. To clear the SWDTE bit by software, read SWDTE when set to 1, then write 0

in the bit.

Bit 7

SWDTE

Description

DTC software activation is disabled

(Initial value)

[Clearing condition]

When the DISEL bit is 0 and the specified number of transfers have not ended

DTC software activation is enabled

[Holding conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

• During software-activated data transfer

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