HD6432138SW datasheet(219/1061 Pages) RENESAS

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Section 7 Data Transfer Controller [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 165 of 1004

REJ09B0301-0400

7.2.3

DTC Source Address Register (SAR)

43210

Bit

Initial value

—

Unde-

fined

Read/write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

7.2.4

DTC Destination Address Register (DAR)

43210

Bit

Initial value

—

Unde-

fined

Read/write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

7.2.5

DTC Transfer Count Register A (CRA)

76543210

CRAH

CRAL

Bit

Initial value

—

Unde-

fined

Read/Write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH)

and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-

bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the

contents of CRAH are transferred when the count reaches H'00. This operation is repeated.

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