HD6432138SW datasheet(129/1061 Pages) RENESAS

129 / 1061 page

Section 3 MCU Operating Modes

Rev. 4.00 Jun 06, 2006 page 75 of 1004

REJ09B0301-0400

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset state is released. It is not initialized in software standby mode.

Bit 0

RAME

Description

On-chip RAM is disabled

On-chip RAM is enabled

(Initial value)

3.2.3

Bus Control Register (BCR)

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

IOS0

R/W

—

R/W

IOS1

R/W

Bit

Initial value

Read/Write

BCR is an 8-bit readable/writable register that specifies the external memory space access mode,

and the I/O area range when the

AS pin is designated for use as the I/O strobe. For details on bits 7

to 2, see section 6.2.1, Bus Control Register (BCR).

BCR is initialized to H'D7 by a reset and in hardware standby mode.

Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the

AS/IOS pin output goes low when IOSE = 1.

BCR

Bit 1

Bit 0

IOS1

IOS0

Description

The

AS/IOS pin output goes low in accesses to addresses

H'(FF)F000 to H'(FF)F03F

The

AS/IOS pin output goes low in accesses to addresses

H'(FF)F000 to H'(FF)F0FF

The

AS/IOS pin output goes low in accesses to addresses

H'(FF)F000 to H'(FF)F3FF

The

AS/IOS pin output goes low in accesses to addresses

H'(FF)F000 to H'(FF)FE4F*

(Initial value)

Note:

In the H8S/2138 F-ZTAT A-mask version, the address range is from H'(FF)F000 to

H'(FF)F7FF.

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