HD6432138SW datasheet(125/1061 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev. 4.00 Jun 06, 2006 page 71 of 1004

REJ09B0301-0400

Section 3 MCU Operating Modes

3.1

Overview

3.1.1

Operating Mode Selection

The H8S/2138 Group and H8S/2134 Group have three operating modes (modes 1 to 3). These

modes enable selection of the CPU operating mode and enabling/disabling of on-chip ROM, by

setting the mode pins (MD1 and MD0).

Table 3.1 lists the MCU operating modes.

Table 3.1

MCU Operating Mode Selection

MCU

Operating

Mode

MD1

MD0

CPU

Operating

Mode

Description

On-Chip

ROM

00—

—

Normal

Expanded mode with on-chip ROM disabled

Disabled

Advanced

Expanded mode with on-chip ROM enabled

Single-chip mode

Enabled

Normal

Expanded mode with on-chip ROM enabled

Single-chip mode

The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2138 Group and

H8S/2134 Group actually access a maximum of 16 Mbytes. However, as there are 16 external

address output pins, advanced mode is enabled only in single-chip mode or in expanded mode

with on-chip ROM enabled when a specific area in the external address space is accessed using

IOS. The external data bus width is 8 bits.

Mode 1 is an externally expanded mode that allows access to external memory and peripheral

devices. With modes 2 and 3, operation begins in single-chip mode after reset release, but a

transition can be made to external expansion mode by setting the EXPE bit in MDCR.

The H8S/2138 Group and H8S/2134 Group can only be used in modes 1 to 3. These means that

the mode pins must select one of these modes. Do not changes the inputs at the mode pins during

operation.

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