HD6432138SW datasheet(131/1061 Pages) RENESAS

131 / 1061 page

Section 3 MCU Operating Modes

Rev. 4.00 Jun 06, 2006 page 77 of 1004

REJ09B0301-0400

Bit 4

IICE

Description

Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used

for SCI1 control register access

(Initial value)

Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used

for SCI2 control register access

Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used

for SCI0 control register access

Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used

for IIC1 data register and control register access

Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used

for PWMX data register and control register access

Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used

for IIC0 data register and control register access

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash

memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control

registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control

registers (PCSR and SYSCR2).

Bit 3

FLSHE

Description

Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register

and supporting module control register access

(Initial value)

Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register

access (F-ZTAT version only)

Bit 2—Reserved: Do not write 1 to this bit.

Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits

CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,

Timer Control Register (TCR).

HD6432138SW Datasheet(PDF) 131 Page - Renesas Technology Corp