HD6432138SW datasheet(110/1061 Pages) RENESAS

110 / 1061 page

Section 2 CPU

Rev. 4.00 Jun 06, 2006 page 56 of 1004

REJ09B0301-0400

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) which contains the

address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address

access, 2 for word access, or 4 for longword access. For word or longword access, the register

value should be even.

• Register indirect with pre-decrement—@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the result becomes the address of a memory operand. The result is

also stored in the address register. The value subtracted is 1 for byte access, 2 for word access,

or 4 for longword access. For word or longword access, the register value should be even.

Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the

absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits

long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).

For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can

access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8

bits are all assumed to be 0 (H'00).

Table 2.5 indicates the accessible absolute address ranges.

Table 2.5

Absolute Address Access Ranges

Absolute Address

Normal Mode

Advanced Mode

Data address

8 bits (@aa:8)

H'FF00 to H'FFFF

H'FFFF00 to H'FFFFFF

16 bits (@aa:16)

H'0000 to H'FFFF

H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32)

H'000000 to H'FFFFFF

Program instruction

address

24 bits (@aa:24)

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