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HD6432138SW Datasheet(PDF) 112 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 112 Page - Renesas Technology Corp |
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112 / 1061 page  Section 2 CPU Rev. 4.00 Jun 06, 2006 page 58 of 1004 REJ09B0301-0400 If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. |
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