HD6432138SW datasheet(995/1061 Pages) RENESAS

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Appendix B Internal I/O Registers

Rev. 4.00 Jun 06, 2006 page 941 of 1004

REJ09B0301-0400

BCR—Bus Control Register

H'FFC6

Bus Controller

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

IOS0

R/W

—

R/W

IOS1

R/W

Bit

Initial value

Read/Write

IOS select

IOS1

Addresses for which AS/IOS is low

output when IOSE = 1

Low output when accessing addresses

H'(FF)F000 to H'(FF)F03F

IOS0

Low output when accessing addresses

H'(FF)F000 to H'(FF)F0FF

Low output when accessing addresses

H'(FF)F000 to H'(FF)F3FF

Low output when accessing addresses

H'(FF)F000 to H'(FF)FE4F*

Burst cycle select 0

Max. 4 words in burst access

Max. 8 words in burst access

Burst cycle select 1

Burst cycle comprises 1 state

Burst cycle comprises 2 states

Burst ROM enable

Basic bus interface

Burst ROM interface

Idle cycle insert 0

Idle cycle not inserted in case of successive

external read and external write cycles

Idle cycle inserted in case of successive

external read and external write cycles

Reserved

Note: * In the H8S/2138 F-ZTAT A-mask version, the address

range is from H'(FF)F000 to H'(FF)F7FF.

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