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HD6432138SW Datasheet(PDF) 997 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 997 Page - Renesas Technology Corp |
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997 / 1061 page  Appendix B Internal I/O Registers Rev. 4.00 Jun 06, 2006 page 943 of 1004 REJ09B0301-0400 TCR0—Timer Control Register 0 H'FFC8 TMR0 TCR1—Timer Control Register 1 H'FFC9 TMR1 TCRX—Timer Control Register X H'FFF0 TMRX TCRY—Timer Control Register Y H'FFF0 TMRY 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 0 CKS0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W Bit Initial value Read/Write Clock select 2 to 0 Channel Bit 2 Bit 1 Bit 0 CKS2 0 1 X Y All 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 CKS1 CKS0 Description Clock input disabled Internal clock: counting at falling edge of φ/8 Internal clock: counting at falling edge of φ/2 Internal clock: counting at falling edge of φ/64 Internal clock: counting at falling edge of φ/32 Internal clock: counting at falling edge of φ/1024 Internal clock: counting at falling edge of φ/256 Counting at TCNT1 overflow signal*2 Clock input disabled Internal clock: counting at falling edge of φ/8 Internal clock: counting at falling edge of φ/2 Internal clock: counting at falling edge of φ/64 Internal clock: counting at falling edge of φ/128 Internal clock: counting at falling edge of φ/1024 Internal clock: counting at falling edge of φ/2048 Count at TCNT0 compare match A*2 Clock input disabled Internal clock: counting on φ Internal clock: counting at falling edge of φ/2 Internal clock: counting at falling edge of φ/4 Clock input disabled Clock input disabled Internal clock: counting at falling edge of φ/4 Internal clock: counting at falling edge of φ/256 Internal clock: counting at falling edge of φ/2048 Clock input disabled External clock: counting at rising edge External clock: counting at falling edge External clock: counting at both rising and falling edges *1 *1 *1 *1 *1 *1 Notes: 1. 2. Selected by ICKS1 and ICKS0 in STCR. For details, see section 12.2.4, Timer Control Register (TCR). If the clock input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter clear 1 and 0 0 Clear is disabled Cleared on compare match A 0 1 1 Cleared on compare match B 0 Cleared on rising edge of external reset input 1 Timer overflow interrupt enable 0 OVF interrupt request (OVI) is disabled 1 OVF interrupt request (OVI) is enabled Compare match interrupt enable A 0 CMFA interrupt request (CMIA) is disabled 1 CMFA interrupt request (CMIA) is enabled Compare Match Interrupt Enable B 0 CMFB interrupt request (CMIB) is disabled 1 CMFB interrupt request (CMIB) is enabled |
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