| Electronic Components Datasheet Search |
|
HD6432138SW Datasheet(PDF) 992 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6432138SW Datasheet(HTML) 992 Page - Renesas Technology Corp |
|
992 / 1061 page ![]() Appendix B Internal I/O Registers Rev. 4.00 Jun 06, 2006 page 938 of 1004 REJ09B0301-0400 STCR—Serial Timer Control Register H'FFC3 System 7 — 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 0 ICKS0 0 R/W 2 — 0 R/W 1 ICKS1 0 R/W Bit Initial value Read/Write Notes: 1. 2. Internal Clock Source Select 1 and 0*1 Reserved Flash memory control register enable 0 Flash memory control register not selected 1 Flash memory control register selected I2C master enable 0 CPU access to SCI0, SCI1, and SCI2 control registers is enabled 1 CPU access to I2C bus interface data, PWMX data registers and control registers is enabled I2C transfer select 1 and 0*2 Reserved Used for 8-bit timer input clock selection. For details, see section 12.2.4, Timer Control Register (TCR). Used for I2C bus interface transfer clock selection. For details, see section 16.2.4, I2C Bus Mode Register (ICMR). |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |