HD6432138SW datasheet(661/1061 Pages) RENESAS

661 / 1061 page

Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)

Rev. 4.00 Jun 06, 2006 page 607 of 1004

REJ09B0301-0400

Figure 21.14 shows the flash memory state transition diagram.

RD VF PR ER FLER = 0

Error

occurrence*1

RES = 0 or STBY = 0

RES = 0 or

STBY = 0

RD VF PR ER FLER = 0

Program mode

Erase mode

Reset or hardware standby

(hardware protection)

RD VF*4

PR ER FLER = 1

RD VF PR ER FLER = 1

Error protection mode

Error protection

mode (software standby,

sleep, subsleep, and watch )

Software standby,

sleep, subsleep, and

watch mode

FLMCR1, FLMCR2 (except

FLER bit), EBR1, EBR2

initialization state*3

FLMCR1,

FLMCR2,

EBR1, EBR2

initialization

state

Software standby,

sleep, subsleep, and

watch mode release

RD: Memory read possible

VF: Verify-read possible

PR: Programming possible

ER: Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

Legend:

RES = 0 or

STBY = 0

Error occurrence*2

Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is

executed for a transition to subactive mode

2. When an error occurs due to a SLEEP instruction (except subactive mode)

3. Except sleep mode

VF in subactive mode

Figure 21.14 Flash Memory State Transitions

HD6432138SW Datasheet(PDF) 661 Page - Renesas Technology Corp

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