HD6432138SW datasheet(520/1061 Pages) RENESAS

520 / 1061 page

Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 466 of 1004

REJ09B0301-0400

Bit 7

MLS

Description

MSB-first

(Initial value)

LSB-first

Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data

and the acknowledge bit, in master mode with the I

2C bus format. When WAIT is set to 1, after the

fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins

(with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the

acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred

consecutively with no wait inserted.

The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the

WAIT setting.

The setting of this bit is invalid in slave mode.

Bit 6

WAIT

Description

Data and acknowledge bits transferred consecutively

(Initial value)

Wait inserted between data and acknowledge bits

Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel

1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode.

They should be set according to the required transfer rate.

HD6432138SW Datasheet(PDF) 520 Page - Renesas Technology Corp