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HD6432138SW Datasheet(PDF) 516 Page - Renesas Technology Corp

Part # HD6432138SW
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1061 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 516 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 462 of 1004
REJ09B0301-0400
TDRE
Description
0
The next transmit data is in ICDR (ICDRT), or transmission cannot
(Initial value)
be started
[Clearing conditions]
• When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)
• When a stop condition is detected in the bus line state after a stop condition is
issued with the I
2C bus format or serial format selected
• When a stop condition is detected with the I2C bus format selected
• In receive mode (TRS = 0)
(A 0 write to TRS during transfer is valid after reception of a frame containing an
acknowledge bit)
1
The next transmit data can be written in ICDR (ICDRT)
[Setting conditions]
• In transmit mode (TRS = 1), when a start condition is detected in the bus line state
after a start condition is issued in master mode with the I
2C bus format or serial
format selected
• At the first transmit mode setting (TRS = 1) (first transmit mode setting only) after
the mode is switched from I
2C bus mode to formatless mode.
• When data is transferred from ICDRT to ICDRS
(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
• When detecting a start condition and then switching from slave receive mode (TRS
= 0) state to transmit mode (TRS = 1) (first transmit mode switching only).
RDRF
Description
0
The data in ICDR (ICDRR) is invalid
(Initial value)
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive mode
1
The ICDR (ICDRR) receive data can be read
[Setting condition]
When data is transferred from ICDRS to ICDRR
(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and
RDRF = 0)



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