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HD6432138SW Datasheet(PDF) 451 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 451 Page - Renesas Technology Corp |
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451 / 1061 page ![]() Section 15 Serial Communication Interface (SCI, IrDA) Rev. 4.00 Jun 06, 2006 page 397 of 1004 REJ09B0301-0400 Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.8, Bit Rate Register. Bit 1 Bit 0 CKS1 CKS0 Description 00 φ clock (Initial value) 1 φ/4 clock 10 φ/16 clock 1 φ/64 clock 15.2.6 Serial Control Register (SCR) 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 0 CKE0 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Bit Initial value Read/Write SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. |
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