HD6432138SW datasheet(454/1061 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 4.00 Jun 06, 2006 page 400 of 1004

REJ09B0301-0400

Bit 2

TEIE

Description

Transmit-end interrupt (TEI) request disabled*

(Initial value)

Transmit-end interrupt (TEI) request enabled*

Note:

TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then

clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock

source and enable or disable clock output from the SCK pin. The combination of the CKE1 and

CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or

the serial clock input pin.

The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in

asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of

external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out

before the SCI’s operating mode is determined using SMR.

For details of clock source selection, see table 15.9 in section 15.3, Operation.

Bit 1

Bit 0

CKE1

CKE0

Description

Asynchronous mode

Internal clock/SCK pin functions as I/O port*

Synchronous mode

Internal clock/SCK pin functions as serial clock

output*

Asynchronous mode

Internal clock/SCK pin functions as clock output*

Synchronous mode

Internal clock/SCK pin functions as serial clock

output

Asynchronous mode

External clock/SCK pin functions as clock input*

Synchronous mode

External clock/SCK pin functions as serial clock

input

Asynchronous mode

External clock/SCK pin functions as clock input*

Synchronous mode

External clock/SCK pin functions as serial clock

input

Notes: 1. Initial value

2. Outputs a clock of the same frequency as the bit rate.

3. Inputs a clock with a frequency 16 times the bit rate.

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