HD6432138SW datasheet(449/1061 Pages) RENESAS

449 / 1061 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 4.00 Jun 06, 2006 page 395 of 1004

REJ09B0301-0400

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is

performed in transmission, and parity bit checking in reception. In synchronous mode, or when a

multiprocessor format is used, parity bit addition and checking is not performed, regardless of the

PE bit setting.

Bit 5

Description

Parity bit addition and checking disabled

(Initial value)

Parity bit addition and checking enabled*

Note:

When the PE bit is set to 1, the parity (even or odd) specified by the O/

E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity

(even or odd) specified by the O/

E bit.

Bit 4—Parity Mode (O/

EEEE): Selects either even or odd parity for use in parity addition and

checking.

The O/

E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and

checking, in asynchronous mode. The O/

E bit setting is invalid in synchronous mode, when parity

bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is

used.

Bit 4

Description

Even parity*

(Initial value)

Odd parity*

Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

2. When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

HD6432138SW Datasheet(PDF) 449 Page - Renesas Technology Corp