HD6432138SW datasheet(413/1061 Pages) RENESAS

Part #	HD6432138SW

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1061 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 13 Timer Connection [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 359 of 1004

REJ09B0301-0400

Table 13.5

Examples of TCR and TCSR Settings

Bit(s)

Abbreviation

Contents

Description

TCR in TMR1

CMIEB

6CMIEA

5OVIE

Interrupts due to compare-match and

overflow are disabled

4 and 3 CCLR1, CCLR0

TCNT is cleared by the rising edge of

the external reset signal (inverted IVI

signal)

2 to 0

CKS2 to CKS0

101

TCNT is incremented on the rising

edge of the external clock (IHI signal)

TCSR in TMR1

3 to 0

OS3 to OS0

0011

Not changed by compare-match B;

output inverted by compare-match A

(toggle output): division by 512

1001

when TCORB < TCORA, 1 output on

compare-match B, and 0 output on

compare-match A: division by 256

TCR in FRT

IEDGB

0/1

0: FRC value is transferred to ICRB

on falling edge of input capture

input B (IHI divided signal

waveform)

1: FRC value is transferred to ICRB

on rising edge of input capture

input B (IHI divided signal

waveform)

1 and 0 CKS1, CKS0

FRC is incremented on internal

clock:

φ/8

TCSR in FRT

CCLRA

FRC clearing is disabled

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