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HD6432138SW Datasheet(PDF) 377 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 377 Page - Renesas Technology Corp |
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377 / 1061 page  Section 12 8-Bit Timers Rev. 4.00 Jun 06, 2006 page 323 of 1004 REJ09B0301-0400 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function] 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 0 IS 0 R/W 2 — 1 — 1 — 1 — Bit Initial value Read/Write TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the counter. TISR is initialized to H'FE by a reset and in hardware standby mode. Bits 7 to 1—Reserved: Do not write 0 to these bits. Bit 0—Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer clock/reset input pin (VSYNCI/TMIY (TMCIY/TMRIY)) as the external clock/reset signal source for the counter. Bit 0 IS Description 0 IVG signal is selected (H8S/2138 Group) External clock/reset input is disabled (H8S/2134 Group) (Initial value) 1 VSYNCI/TMIY (TMCIY/TMRIY) is selected |
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