HD6432138SW datasheet(373/1061 Pages) RENESAS

373 / 1061 page

Section 12 8-Bit Timers

Rev. 4.00 Jun 06, 2006 page 319 of 1004

REJ09B0301-0400

12.2.6

Serial Timer Control Register (STCR)

—

R/W

IICX1

R/W

IICX0

R/W

IICE

R/W

FLSHE

R/W

ICKS0

R/W

—

R/W

ICKS1

R/W

Bit

Initial value

Read/Write

STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode

(when the on-chip IIC option is included), and on-chip flash memory (in F-ZTAT versions), and

also selects the TCNT input clock.

For details on functions not related to the 8-bit timers, see section 3.2.4, Serial Timer Control

not used, do not write 1 to the corresponding bit.

STCR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—Reserved: Do not write 1 to this bit.

Bits 6 to 4—I

2C Control (IICX1, IICX0, IICE): These bits control the operation of the I2C bus

interface when the IIC option is included on-chip. See section 16.2.7, Serial Timer Control

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash

memory control registers, the power-down mode control registers, and the supporting module

control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details.

Bit 2—Reserved: Do not write 1 to this bit.

Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits

CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,

Timer Control Register.

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