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ADE3800 Datasheet(PDF) 96 Page - STMicroelectronics |
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ADE3800 Datasheet(HTML) 96 Page - STMicroelectronics |
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96 / 138 page ![]() Register Description by Block ADE3800 96/138 The omux architecture consists of 2 main blocks as shown in Figure 19. OMUX_CTRL7 0C37 R/W [7] 00 1: invert RSDS clock 1 (RSDS data pair 12) R/W [6] 0*: normal LVDS PLL clock if LVDS mode (normal) 1: invert LVDS PLL clock if LVDS mode, or invert RSDS clock 0 (RSDS data pair 21) if RSDS mode R/W [4] 1: invert LVDS output DE R/W [1] [0] TCON remapped to PWM TCON[1] = pwm_a enable TCON[0] = pwm_b enable OMUX_HALF_LINE_L OMUX_HALF_LINE_U 0C38 0C39 R/W R/W [7:0] [3:0] 00 00 RSDS split buffer half line address = out_hpixel/2. out_hpixel has to be multiples of 4. E.g. for SXGA panel (1280) the value is 640 OMUX_TEST 0C3A R/W [1] 00 1: enable RSDS debug mode R/W [0] 1: enable LVDS debug mode Table 34: OMUX_CTRL Output Modes OUTPUT MODE OMUX_CTRL1 [0] OMUX_CTRL3 [0] idle 0 0 LVDS mode 1 0 RVDS mode 0 1 Figure 19: OMUX Architecture Table 33: OMUX Registers (Sheet 3 of 3) Register Name Addr Mode Bits Rst Description |
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