ST10 datasheet(30/65 Pages) STMICROELECTRONICS

30 / 65 page

ST10C167

30/65

XVIII - POWER REDUCTION MODES

Two different power reduction modes with differ-

ent levels of power reduction can be entered

under software control.

In Idle mode the CPU is stopped, while the

peripherals continue their operation. Idle mode

can be terminated by any reset or interrupt

request.

In Power Down mode both the CPU and the

peripherals are stopped. Power Down mode can

be configured by software in order to be termi-

nated only by a hardware reset or by an external

interrupt source on fast external interrupt pins.

There are two different operating Power Down

modes:

– Protected power down mode: selected by set-

ting bit PWDCFG in the SYSCON register to ‘0’.

This mode can be used in conjunction with an

external power failure signal which pulls the NMI

pin low when a power failure is imminent. The

microcontroller enters the NMI trap routine and

saves the internal state into RAM. The trap rou-

tine then sets a flag or writes a bit pattern into

specific RAM locations, and executes the

PWRDN instruction. If the NMI pin is still low at

this time, Power Down mode will be entered, if

not program execution continues. During power

down the voltage at the VCC pins can be lowered

to 2.5 V and the contents of the internal RAM will

still be preserved.

– Interruptible

power

down

mode:

this

mode is selected by setting bit PWDCFG in the

SYSCON register. The CPU and peripheral

clocks are frozen, and the oscillator and PLL are

stopped. To exit power down mode with an ex-

ternal interrupt, an EXxIN (x = 7...0) pin has to

be asserted for at least 40ns. This signal ena-

bles the internal oscillator and PLL circuitry, and

turns on the weak pull-down. If the Interrupt was

enabled before entering power down mode, the

device executes the interrupt service routine,

and then resumes execution after the PWRDN

instruction. If the interrupt was disabled, the de-

vice executes the instruction following PWRDN

instruction, and the Interrupt Request Flag re-

mains set until it is cleared by software.

All external bus actions are completed before Idle

or Power Down mode is entered. However, Idle or

Power Down mode is not entered if READY is

enabled, but has not been activated during the

last bus access.

ST10 Datasheet(PDF) 30 Page - STMicroelectronics

ST10 Datasheet(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL